1. Field of the Invention
The present invention relates to an electronic component and a manufacturing method thereof.
2. Description of the Related Art
In order to achieve downsizing and sophistication of semiconductor devices, there exists a practical application of a package structure (known as a chip-on-chip (COC) structure) in which a plurality of semiconductor chips are stacked and sealed inside a single package. A COC package is applied in a structure having logical elements and high-capacity memory chips stacked together. Moreover, research is being pursued toward the practical application of a COC package as a system-in-package (SiP) type semiconductor device. Meanwhile, regarding the connection between stacked semiconductor chips, application of flip-chip interconnection is being examined with the object of increasing the speed of data transmission (e.g., see Japanese Patent Application Laid-open No. 2009-38266).
As a stacked type semiconductor device, there exists a configuration in which a first semiconductor chip is bonded using an adhesive agent to the top face of an interconnection substrate having pads and solder balls arranged on the bottom face thereof and a second semiconductor chip is mounted on the first semiconductor chip. Land electrodes are arranged on the periphery of the top face of the interconnection substrate, and connected to first pads arranged on the periphery of the top face of the first semiconductor chip by a wire bonding. Bumps are formed on the bottom face of the second semiconductor chip, and connected to second pads formed on the top face of the first semiconductor chip by a flip-chip bonding. Between the first semiconductor chip and the second semiconductor chip is filled an underfill material. Besides, the first semiconductor chip and the second semiconductor chip on the top face of the interconnection substrate are resin-sealed. In such a configuration, the use of flip-chip interconnection enables achieving reduction in the connection distance between the semiconductor chips. Hence, it becomes possible, for example, to increase the speed of data transmission between memory chips and logical elements.
Meanwhile, a semiconductor chip having thousands of bumps formed on the bottom face thereof has come into practical use in a SiP type semiconductor device. Such semiconductor chips including thousands of bumps are made to be increasingly thinner and the warpage thereof is causing occurrence of bumps that are not connectable with interconnection substrates or with other semiconductor chips. Thus, in regard to performing flip-chip interconnection with the use of bumps, a technology has been disclosed by which, even if a semiconductor chip has a warpage, the height of bumps is changed within the plane of the semiconductor chip in such a way that all of the bumps get connected (e.g., see Japanese Patent Application Laid-open No. 2004-335660). In this way, methods have been proposed in the past for resolving the issue of poor connection of bumps that is caused by the differences occurring in bump formation positions prior to flip-chip interconnection due to the warpage of a semiconductor chip. However, no particular consideration has been given to the issue of differences in the height of bumps occurring during bump formation.